A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter

T RADITIONAL designs of high-speed CMOS analogto-digital (A/D) converters have used parallel (flash) architectures [1]–[13]. While flash architectures usually yield the highest throughput rate, they tend to require large silicon. areas because of the many comparators required. An important objective is the realization of high-speed A/D converters in much less area than that required by flash converters so that the A/D interface function can be integrated on the same chip with associated complex, high-speed, image-processing functions. Multistage conversion architectures reduce the required area by reducing the total number of comparators [14]–[19]. Using a pipelined mode of operation in these architectures allows the stages to operate concurrently and makes the maximum throughput rate almost independent of the number of stages. Also, digital correction techniques significantly reduce the sensitivity of the architecture to certain component nonidealities. Pipelined configurations have been previously applied in high-performance board-level converters, but they have not been applied to monolithic CMOS A/D converters because of the difficulty of realizing high-speed interstage sample-and-hold (S/H) gain functions in CMOS technologies. In this paper, an experimental four-stage pipelined A/D converter with digital correction that has 9-bit resolution and 5-Msample/s conversion rate in a 3-pm CMOS technology is described. The experimental converter uses high-speed differential switched-capacitor circuitry to carry out the interstage gain functions. This paper is divided into four additional parts. In Section II, pipelined A/D architectures are described con-